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Ordering number : ENN*6830
CMOS IC
LC680100A
32-Bit RISC Microcontroller
Preliminary Overview
The LC680100A is a 32 bit microcontroller developed exclusively by Sanyo, based on a 32 bit RISC CPU and incorporating on a single chip a high speed multiplier, 2kB of cache RAM, 2kB data RAM, DRAM control unit, external memory control unit and peripheral It is an ideal control device for digital cameras, color printers and hand held data terminals.
Features
(1) CPU core :32 bit RISC (Speed: 15MHz, Instruction cycle time: 67ns) (2) High Speed Multiplier :16bit x 16bit (in 1 instruction cycle) (3) Instruction cache RAM :2kB (512x32bit) (4) Data RAM :2kB (512x32bit) (5) DRAM Control Unit (6) External memory bus control unit (7) I/O port :One 16 bit I/O port, one 8 bit I/O port (8) UART :Two full duplex asynchronous channels (one channel has 16bit FIFO) (9) Serial I/O :One three-wire synchronous clock, 8 bit (10) Timer :4 channels (TM0 = 16bit + 16bit) (TM1, TM2, TM3 = 8bit + 8bit) (11) PWM Output :Three 8 bit resolution outputs (Common with TM1, TM2, TM3) (12) Interrupt controller :13 source events (5 internal, 8 external), 5 vectored (13) OSC circuit :Two types: main and RC. VCO/PLL is built-in, frequency multiplication possible. (14) Standby :Standby (HOLD) and sleep (HALT) modes available (15) VDD :3.3V typ.
Package and Pins
SQFP100, 100 pins
Development tools
A C compiler, assembler and emulator are available to be run on a PC.
Ver.1.2 D0798
N3000 RM (IM) IT No.6830-1/16
LC680100A
System Block Diagram
Instruction Cache Main OSC (2k bytes)
Multiplier Circuit
Instruction Cache Control
RC OSC
System Clock, Standby Control 32bit RISC CORE Data RAM Mode Control Reset Control (2k bytes) Bus Control
Coprocessor (Multiplier)
DRAM Control
Interrupt Control
Interrupt enable control
TM0H TM0L TM1H TM2H TM3H SIO0 UART0 UART1
Special Function Register SFR Bus Control
SIO0
Timer 0
UART0
Timer 1
UART1
Timer 2
Port 0
Timer 3
Port 1
Figure 1 LC680100A System Block Diagram
No.6830-2/16
LC680100A
Terminal Assignment Diagram
(SQFP100, 0.5mm pitch)
A27/CS3
A26/CS4
A25/CS5 A24
A23
A22
A19 A18
A17
A16
A15 A14
A12 A11
VDD
VSS
A21 A20
A13
A10
D1
D0
A9 A8
D2 D3 D4 D5 D6 D7 VDD D8 D9 D10 D11 D12 D13 D14 D15 VSS CS0 CS1 CS2 CS6 RD WRU/UBS WRL/WR WAIT BREQ
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 77 49 78 48 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A7
A6 A5 A4 A3 A2 A1 A0/LBS VSS P17/MCLK/HOLDO P16/IRQOT P15/RFREQ P14/DMXS P13/CASL P12/CASU P11/RAS P10/BGNT VDD NMI P0F P0E P0D/RXD1 P0C/TXD1 P0B/PWM2 P0A/INT3 P09/INT2
LC680100A
345
P04/SCK P05/PWM0
P06/PWM1
RESET
MODE
CKOT
P01/RXD0 P02/SDO
P00/TXD0
CMP
VDD
VDD CK1
HOLDI
VSS PHIOT
TEST
VDD
VSS
CKIN
CK2
P07/T0IN/INT0
VSS
Package Dimension (unit : mm)
3181B
P08/INT1
P03/SDI
SANYO : SQFP-100
No.6830-3/16
LC680100A
Terminal Functions
Pin Number 1,6,15,34,55 VDD ,82 4,9,24,43,73 VSS ,91 2 3 5 7 8 10 11 12 13 14 16 17 18 19 20 21 22 23 CK1 CK2 CMP CKOT CKIN
PHIOT HOLDI RESET
Note: PU = pull-up
I/O I O I/O O I O I I I I I/O I/O I/O I/O I/O I/O I/O I/O Function Description Power supply +ve Power supply -ve Input to main oscillator Output from main oscillator Phase comparator filter pin (multiplier circuit). Schmitt Input CMOS output Schmitt Input*Tristate output Schmitt Input CMOS output Schmitt Input Schmitt Input Schmitt Input Schmitt Input *Used as input: Schmitt Input; presence of PU resistor software selectable. *Used as Output: CMOS/N-ch OD mode software selectable. Pin Format
Pin Name
CK1 or half frequency clock output from multiplier CMOS output External clock input System clock output HOLD request input Reset terminal Bus mode setting at reset Test input (Normally connected to VSS) PORT0 bit0 I/O. Also UART0 send PORT0 bit1 I/O. Also UART0 receive PORT0 bit2 I/O. Also SIO0 data out PORT0 bit3 I/O. Also SIO0 data in PORT0 bit4 I/O. Also SIO0 clock PORT0 bit5 I/O. Also PWM0 output PORT0 bit6 I/O. Also PWM1 output PORT0 bit7 I/O. Timer0 event input INT0 input PORT0 bit8 I/O. INT1 input PORT0 bit9 I/O. INT2 input PORT0 bit10 I/O. INT3 input PORT0 bit11 I/O. PWM2 output PORT0 bit12 I/O. UART1 send PORT0 bit13 I/O. UART1 receive PORT0 bit14 I/O. PORT0 bit15 I/O.
MODE TEST P00/TXD0 P01/RXD0 P02/SDO P03/SDI P04/SCK P05/PWM0 P06/PWM1 P07/T0IN/INT0
25 26 27 28 29 30 31 32
P08/INT1 P09/INT2 P0A/INT3 P0B/PWM2 P0C/TXD1 P0D/RXD1 P0E P0F
I/O I/O I/O I/O I/O I/O I/O I/O
No.6830-4/16
LC680100A
Pin Number 33 35 36 37 38 39 40 41 42
NMI
Pin Name
I/O I I/O I/O I/O I/O I/O I/O I/O I/O NMI interrupt
Function Description
Pin Format Schmitt Input Schmitt Input*Tristate output
P10/BGNT P11/RAS P12/CASU P13/CASL P14/DMXS P15/RFREQ P16/IRQOT P17/MCLK/HOLD0
PORT1 bit0 input. Also bus grant output. PORT1 bit1 input. Also DRAM control RAS signal out. PORT1 bit2 input. Also DRAM control CASU signal out. PORT1 bit3 input. Also DRAM control CASL signal out. PORT1 bit4 input. Also DRAM control DMXS signal out. PORT1 bit5 input. Also DRAM control RFREQ I/O. PORT1 bit6 input. Also IRQOT output. PORT1 bit7 input. MCLK output, HOLD state output Bus Address bit0 or Lower byte strobe signal. Bus Address bit1 to 24. Bus Address bit25 Bus Address bit26 Bus Address bit27 Bus data bit0 to 15
CS0 CS1 CS2 CS6
Schmitt Input*PU Output Schmitt Input*Tristate output
44 45 to 54, 56 to 69 70 71 72 74 to 81, 83 to 90 92 93 94 95 96 97 98 99 100
A0/LBS A1to A24 A25/CS5 A26/CS4 A27/CS3 D0 to D15
CS0 CS1 CS2 CS6 RD WRU/UBS WRL/WR WAIT BREQ
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
Schmitt Input*Tristate output
or or or
CS5. CS4 CS3. Schmitt Input*Tristate output Schmitt Input*Tristate output
Bus read signal. Upper byte write signal Upper byte write signal Bus cycle wait Bus request. or or Upper byte strobe. Write.
Schmitt Input*Tristate output
Schmitt Input*PU output Schmitt Input
No.6830-5/16
LC680100A 1. Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol VDD
Pins
Conditions
Ratings
Unit
Supply voltage Input voltage Output voltage Input/Output voltage High level peak output current High level total output current Low level peak output current Low level total output current Maximum power consumption Operating temperature range Storage temperature range
VDDmax VI(1) VO(1) VIO(1) IOPH(1) IOAH(1) IOAH(2) IOPL(1) IOAL(1) IOAL(2) Pdmax Topg Tstg
Note1 Pins for each input only Pins for each output only Pins for both input and output Each output pin P00 to P08 P09 to P0F Each output pin P00 to P07 P08 to P0F SQFP100 Note2 Current at each pin Total of 9 pins Total of 7 pins Current at each pin Total of 8 pins Total of 8 pins Ta = -20 to 70C
-0.3 to +4.6 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -5 -80 -80 20 80 80 440 -20 to +70 -55 to +125
V V V V mA mA mA mA mA mA mW C C
Note1:All VDD terminals (pin1, 6, 15, 34, 55, 82) should be connected externally. All VSS terminals (pin4, 9, 24, 43, 73, 91) should be connected externally. Note2:Reflow method is recommended when soldering the SQFP package.
No.6830-6/16
LC680100A 2. Recommended Operating Range at Ta = -20 to 70C, VSS = 0V
Parameter Operating supply voltage range Supply voltage (Memory hold) High level input voltage Low level input voltage
Symbol
Pins
Conditions Min.
Ratings Typ. 3.3 Max. 3.6 3.6 VDD VDD 0.3VDD 0.3VDD 3333 5000 15M 15M
Unit
VDD (1) VHD VIH(1) VIH(2) VIL(1) VIL(2) tCYC(1)
VDD VDD Input pins except CK1 CK1 Input pins except CK1 CK1 CKIN CK1 CKIN CK1 CKIN CK1 300K to 15MHz 400K to 15MHz (VCO is not used.) Figure 1 Figure 1 Figure 1 Figure 1 Keep RAM and Register data in Standby mode.
3.0 2.5 0.7VDD 0.7VDD VSS VSS 66 132 300k 400k 28
V V
V
V
Operation cycle time
tCYC(2) fEXCKIN fEXCK1 tCKINL tCKINH tCK1L tCK1H tEXR tEXF
ns
External system clock frequency External clock pulse width
Hz
ns 28
External clock rising and falling time Operation frequency range
CKIN, CK1
Figure 1
5
ns
fCK1
CK1, CK2
Figure 2, Table 1
400k
8M
Hz
No.6830-7/16
LC680100A 3. Electrical Characteristics at Ta = -20 to 70C, VSS = 0V, VDD = 3.0 to 3.6V
Parameter
Symbol
Pins Pins for each input only Pins for both input and output Pins for each input only P15/RFREQ,WAIT Input/output commonly terminals except written above Port0 with PU option, P15/RFREQ Input/output commonly terminals except written above, CKOT, PHIOT Pins for each output only Pins for both input and output Port0 with PU option, P15/RFREQ Each input only, I/O terminal
NMI
Conditions Min.
Ratings Typ. Max. 5
Unit
High level input current
IIH(1) IIH(2) IIL(1)
VIN = VDD VIN = VDD Output disabled VIN = VSS VIN = VSS Output disabled VIN = VSS Output disabled IOH = -0.05mA -5 -5
A 5
Low level input current
IIL(2)
A
IIL(3)
-5
VOH(1) High level output voltage
VDD-0.5 V
VOH(2)
IOH = -1mA
VDD-0.5
Low level output voltage
VOL(1) VOL(2) rPU vHIS tINTL tINTH tRESL fVCO tLOCK fRC tCF IDDRUN IDDSLP IDDSTY cP
IOL = 4mA IOL = 4mA 1K 0.1 Figure 4 Figure 4 Figure 5 Figure 5, cCMP = 0.1F 300k Figure 3 CKIN=15MHz 60 50 10 10 2 4 2 4M 10
0.4 V 0.4 20K VDD Tcyc ms 16M Hz ms 1M 10 120 100 200 Hz ms mA mA A PF
PU resistor Hysterisis voltage External interrupt pulse width Reset input pulse width VCO frequency VCO lock-up time RC oscillation frequency Ceramic oscillation stabilizing time Current consumption in run mode Current consumption in sleep mode Current consumption in standby mode Pin capacitance
INT0 to INT3
RESET
CKOT CMP,CKOT Built-in RC oscillation circuit CK1,CK2 VDD VDD VDD All pins
No.6830-8/16
LC680100A 4. Serial Input/Output Characteristics at Ta = -20 to 70C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14
Parameter Input clock cycle time Input clock L pulse width Input clock H pulse width Output clock cycle time Output clock L pulse width Output clock H pulse width Input data set up time Input data hold time Output delay time
Symbol tSCK tSCKL tSCKH tSCKO tSCKOL tSCKOH tsDI thDI tdDO
Pins
SCK input SCK input SCK input SCK output SCK output SCK output SCK, SDI SCK, SDI SCK, SDO
Conditions Min. Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 16 533 533 16 8 8 200 50
Ratings Typ. Max.
Unit Tcyc ns ns Tcyc Tcyc Tcyc ns ns
100
130
ns
No.6830-9/16
LC680100A 5. Bus Timing at Ta = -20 to 70C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure14
Parameter Address output delay time Address output hold time CS delay time (1) CS hold time (1) RD delay time (1) RD hold time (1) Read data set up time (1) Read data hold time (1) WR delay time (1) WR hold time (1) Write data delay time (1) Write data hold time (1) Bus request input setup time Bus request input hold time BGNT output delay time Bus release delay time WAIT set up time WAIT input hold time
Symbol
Pins
Conditions Min. Figure 7, Figure 8 Figure 7, Figure 8 Figure 7, Figure 8 Figure 7, Figure 8 Figure 7 Figure 7 Figure 7 Figure 7 Figure 8 Figure 8 Figure 8 Figure 8 Figure 12 Figure 12 Figure 12 Figure 12 30 30 0 30 30 30 0
Ratings Typ. Max. 75 75
Unit
tAAD tADA tACS tCSA tARD tRDA tsRD1 thRD1 tAWR tWRA tdWD1 thWD1 tsBRQ thBRQ tdBGT tdBOF tsWAIT thWAIT
A27 to A0 A27 to A0
CSn CSn RD RD
ns 45 55 45 55 ns
D15 to D0 D15 to D0,
WRU, WRL WRU, WRL
45 55 70 30 ns
D15 to D0, WRU , WRL D15 to D0, WRU, WRL CKIN, BREQ CKIN, BREQ CKIN, BGNT CKIN, A27 to A0,
RD ,WRU ,WRL
50 50
ns
CKIN, WAIT CKIN, WAIT
No.6830-10/16
LC680100A 6. DRAM Timing at Ta = -20 to 70C, VSS = 0V, VDD = 3.0 to 3.6V, with the load in Figure 14
Ratings Min. Address (ROW) delay time Address (COL) delay time Address (COL) hold time RAS delay time RAS hold time DMXS delay time DMXS hold time CASL*CASU delay time CASL*CASU hold time Read data set up time (2) Read data hold time (2) WRL*WRU delay time WRL*WRU hold time Write data delay time (2) Write data hold time (2) tAROW tACOL tCOLA tARAS tRASA tDMXSR tDMXSC
tACAS(L/U)
Parameter
Symbol
Pins
Conditions
Unit Max. 75 55 70 65 50 70 50 65 50 ns
Typ.
A27 to A0 A27 to A0 A27 to A0
RAS RAS
Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9, Figure 10 Figure 9 Figure 9 Figure 10 Figure 10 Figure 10 Figure 10 0 30
DMXS DMXS
CASU, CASL CASU, CASL
tCAS(L/U)A
tsRD2 thRD2 tAWR(L/U) tWR(L/U)A tdWD2 thWD2
D15 to D0 D15 to D0, RD
WRU, WRL WRU, WRL
ns 0 45 50 70 ns
D15 to D0,
WRU, WRL
D15 to D0,
WRU, WRL
Table 1. Guaranteed Value for the Ceramic Oscillators
Oscillator 4MHZ (External Capacitor) 4MHZ (Capacitor built-in) 8MHZ (External Capacitor) 8MHZ (Capacitor built-in) Manufacturer Murata Oscillator CSA4. OOMG CST4. OOMGW CSA8. OOMTZ CST8. OOMTW 33pF (30pF) 33pF (30pF) C1 33pF (30pF) 33pF (30pF) C2
No.6830-11/16
LC680100A Figure1 External Clock Input
1/fEXCKIN or 1/fEXCK1 External Input CK1 0.8VDD 0.2VDD CK2 CKIN
External Input
tCKINL or tCK1L
tCKINH or tCK1H
Figure2 Ceramic Oscillation
Figure3 Oscillation Stabilizing Time
C1 Oscillator
CK1
VDD
VDD lowest limit
CK2 C2 CK2 Stabilized oscillation tCF
Figure4 External Pulse Input
Figure5 VCO
Phase Compare
0.5VDD cCMP tINTL tRESL tINTH CMP VCO 1/2
VCOSW
CKOT
Figure6 Serial Input/Output Timing
tSCK or tSCKO tSCKL OR tSCKOL
SCK
tSCKH OR tSCKOH 0.5VDD
tsDI
thDI
SDI
0.5VDD
SDO tdDO
0.5VDD
No.6830-12/16
LC680100A Figure7 External Bus Read Timing
Figure8 External Bus Write Timing
No.6830-13/16
LC680100A Figure9 DRAM Read Timing
Figure10 DRAM Write Timing
No.6830-14/16
LC680100A Figure11 REREQ Input/Output Timing
Figure12 Bus Request/Release Timing
Figure13 Wait Input/Output Timing
Figure14 The Load Used in Measuring the Timing
No.6830-15/16
LC680100A
PS No.6830-16/16

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